I am getting the error message below.
<code>./nand.v:1: syntax error
I give up.
</code>
<code>./nand.v:1: syntax error
I give up.
</code>
./nand.v:1: syntax error
I give up.
Here is my nand.v code:
<code>module nand (A, B, C);
input A, B;
output C;
assign C = ~(A & B);
endmodule
</code>
<code>module nand (A, B, C);
input A, B;
output C;
assign C = ~(A & B);
endmodule
</code>
module nand (A, B, C);
input A, B;
output C;
assign C = ~(A & B);
endmodule
And here is my testbench code:
<code>`timescale 1ns / 1ns
`include "nand.v"
module nand;
reg A;
reg B;
wire C;
nand uut(A,B,C);
initial begin
$dumpfile("nand_tb.vcd");
$dumpvars(0, nand_tb);
A = 0;
B = 0;
#20
A = 1; // 01
B = 0;
#20
A = 0; //10
B = 1;
#20
A = 1;
B = 1; // 11
#20
$display("Test complete");
end
endmodule
</code>
<code>`timescale 1ns / 1ns
`include "nand.v"
module nand;
reg A;
reg B;
wire C;
nand uut(A,B,C);
initial begin
$dumpfile("nand_tb.vcd");
$dumpvars(0, nand_tb);
A = 0;
B = 0;
#20
A = 1; // 01
B = 0;
#20
A = 0; //10
B = 1;
#20
A = 1;
B = 1; // 11
#20
$display("Test complete");
end
endmodule
</code>
`timescale 1ns / 1ns
`include "nand.v"
module nand;
reg A;
reg B;
wire C;
nand uut(A,B,C);
initial begin
$dumpfile("nand_tb.vcd");
$dumpvars(0, nand_tb);
A = 0;
B = 0;
#20
A = 1; // 01
B = 0;
#20
A = 0; //10
B = 1;
#20
A = 1;
B = 1; // 11
#20
$display("Test complete");
end
endmodule
The error points to line 1 but I don’t see why it’s wrong. I am comparing the code to other .v files that I have and nothing seems out of place.
I am compiling with:
<code>iverilog -o nand_tb.vvp nand_tb.v
</code>
<code>iverilog -o nand_tb.vvp nand_tb.v
</code>
iverilog -o nand_tb.vvp nand_tb.v
I looked at other .v files that compiled successfully but I couldn’t find anything wrong with my code.
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