I wrote a VHDL code as follows:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-----------------------------------------------------------------------------------------------------
-- ENTITY DEFINITION                                                                              --
----------------------------------------------------------------------------------------------------

entity controller_1 is
  port(
   clk                    : in std_logic;
   rst                    : in std_logic;
   ls_charge_o            : out std_logic;      
   laser_trg_0_o          : out std_logic;     
   laser_trg_1_o          : out std_logic;      
   laser_en               : out std_logic;
   pwm_duration_1         : in std_logic_vector(15 downto 0);     
   pwm_duration_2         : in std_logic_vector(15 downto 0);     
   pwm_duration_3         : in std_logic_vector(15 downto 0);     
   pwm_duration_4         : in std_logic_vector(15 downto 0);        
   pwm_pattern            : in std_logic_vector(15 downto 0)  
  );

end controller_1 ;


architecture rtl of controller_1 is


--- The registers conversion
signal CYCLES_PWM_DURATION_1         : integer := 0;
signal CYCLES_PWM_DURATION_2         : integer := 0;
signal CYCLES_PWM_DURATION_3         : integer := 0;
signal CYCLES_PWM_DURATION_4         : integer := 0;
signal wait_b4_nxt_shot              : integer := 0;
type t_State is (state_1, state_2, state_3, state_4, state_5, state_6, state_7, state_8, state_9, state_10, state_11, state_12);
signal state : t_State;

begin

CYCLES_PWM_DURATION_1    <=  FREQUENCY_WO_EXP * (to_integer(unsigned(pwm_duration_1)))/1000 ;                  
CYCLES_PWM_DURATION_2    <=  FREQUENCY_WO_EXP * (to_integer(unsigned(pwm_duration_2)))/1000 ;                     
CYCLES_PWM_DURATION_3    <=  FREQUENCY_WO_EXP * (to_integer(unsigned(pwm_duration_3)))/1000 ;                     
CYCLES_PWM_DURATION_4    <=  FREQUENCY_WO_EXP * (to_integer(unsigned(pwm_duration_4)))/1000 ;                                                             
WAIT_B4_NXT_SHOT         <=  (250 *4) - (CYCLES_PWM_DURATION_1 + CYCLES_PWM_DURATION_2 + CYCLES_PWM_DURATION_3 + CYCLES_PWM_DURATION_4);       

The question is, will the signals CYCLES_PWM_DURATION_1, CYCLES_PWM_DURATION_2, CYCLES_PWM_DURATION_3, CYCLES_PWM_DURATION_4, and WAIT_B4_NXT_SHOT get synthesized? So far this approach doesnt seem to work.

It is working in simulation but not on hardware. Synthesis is going fine and bit file it getting generated, though. I am using Lattice FPGA. If you think this will not work, then is there any ulternative approach to this?