I designed a down counter with a clk, set_n, load_data, and timer_on. When I put set_n = 0, the down counter is supposed to load_data, set the timer_on = 1, and then keep decreasing the counter until it reaches 0. However, the simulation does not show that my down_counter is working.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity down_counter is 
    port(   
         clk           : in std_logic;  -- clock input
            set_n       : in std_logic;  -- reset
            load_data     :  in  unsigned(31 downto 0);
            timer_on      : out std_logic -- timer_on = 1 if the counter has not reached 0
    
    );
end down_counter;
    
    architecture rtl of down_counter is 
    
    signal s_counter: unsigned(31 downto 0) := (others => '0');
    
    begin
    
        process (clk, set_n) 
        begin
            if set_n = '0' then
                    s_counter <= load_data;
                    timer_on <= '1';
            elsif rising_edge(clk) then
               if s_counter = 0  then
                        timer_on <= '0';
                        s_counter <= load_data;
               else 
                    s_counter <= s_counter - 1;
                    timer_on <= '1';
                    
                end if;
            end if;
            
                    
        end process; 
                
    end rtl ;

and here is the teste bench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;


entity down_counter_tb is 
end down_counter_tb;


architecture sim of down_counter_tb is 

    component down_counter is 
        port(   
                        clk           : in std_logic;  -- clock input
            set_n         : in std_logic;  -- reset
            load_data     : in  unsigned(31 downto 0);
            timer_on      : out std_logic -- timer_on = 1 if the counter has not reached 0
    
        );
    end component;

    constant clk_period         :   time    := 10 ns; -- clock periods  
   
    signal s_clk:   std_logic   := '0';
    signal s_set_n : std_logic := '1';
    signal s_load_data : unsigned(31 downto 0):= (others => '0');
    signal s_timer_on: std_logic;
     
     
begin
    i_down_counter : down_counter
        port map (s_clk, s_set_n, s_load_data, s_timer_on);
        
        
     -- Clock process definitions
   clk_process :process
   begin
        s_clk <= '1';
        wait for clk_period/2;
        s_clk <= '0';
        wait for clk_period/2;
   end process;
    
    -- Stimulus process
   stim_proc: process
   begin        
        s_set_n<= '1';
        wait for clk_period*10;
        s_set_n <= '0';
        --by setting the input as "10", I want a delay of 10 clock cycles.
        --in real time,the delay = 10*period of clock.
        --so here in simulation, delay = 10*10 ns = 100 ns.
        s_load_data <= to_unsigned(10,32);
      wait;
   end process;
    
end architecture;