this is my module..
reg [2:0]count=3’b0;
reg [l4_offset-1:0]offset; wire [l4_offset-1:0]pseudo_offset;

always@*
begin
if((offset_seqres>=0))
begin
//the chunk it is processing contains next offset…..//…assume next is l3ext…
offset<=offset_seqres;
end
else //offset_seqres<0
begin
for (offset = offset_seqres; offset <= 0; )
begin
count = count + 1;
offset = offset + (`pkt_width/8);
end
end
end

assign pseudo_offset=(((512-1)-(128*count))-(128-offset));

Warning(19637): Verilog HDL warning at l3_des3.v(285): variable count may be used before assigned in always_comb or always @* block : might cause synthesis – simulation differences.
Warning(16788): Net “count[1]” does not have a driver at l3_des3.v(270)
i am getting these two errors. How to resolve it ?