<code>typedef struct packed {
logic [3:0] A;
logic [3:0] B;
} pkt;
rand pkt [10] p;
</code>
<code>typedef struct packed {
logic [3:0] A;
logic [3:0] B;
} pkt;
rand pkt [10] p;
</code>
typedef struct packed {
logic [3:0] A;
logic [3:0] B;
} pkt;
rand pkt [10] p;
How to write constraints to systemverilog so that they are executed simultaneously:
- A and B had unique combinations
- A and B had repeatable data a random number of times.
For example:
A in the range 0-1
B in the range 0-2
maximum number of repetitions = 3
Result:
A = 0, 0, 0, 1, 1, 1, 0, 1, 1, 1 , …
B = 0, 0, 1, 2, 2, 2, 2, 0, 1, 1 , …
I tried to use:
<code>constraint r {
foreach (p[i]) {
p[i].A inside {[0:1]};
p[i].B inside {[0:2]};
unique {p[i].A, p[i].B};
}
}
</code>
<code>constraint r {
foreach (p[i]) {
p[i].A inside {[0:1]};
p[i].B inside {[0:2]};
unique {p[i].A, p[i].B};
}
}
</code>
constraint r {
foreach (p[i]) {
p[i].A inside {[0:1]};
p[i].B inside {[0:2]};
unique {p[i].A, p[i].B};
}
}
But for some reason it doesn’t work.
And I don’t know how to repeat the values. So that “unique ” doesn’t break.
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