I have hundreds of VHDL files and Quartus 24.2 decided to raise errors for hundreds of lines.

CurrentDataset_DatReg.OffsetFromMaster(63 downto 48) <= std_logic_vector((unsigned((not OffsetAdjustment_DatReg.TimeAdjustment.Second))+1));
CurrentDataset_DatReg.OffsetFromMaster(63 downto 48) <= OffsetAdjustment_DatReg.TimeAdjustment.Second;

Error(24543): VHDL error at Ptp_OffsetCalculator.vhd(333): target slice of 16 elements cannot be assigned a value of 32 elements

This code isn’t mine, we bought it few years ago, everything was fine until we had to update Quartus’ version.

I’m not familiar with VHDL, is there a setting or a way to fix all the similar lines?

In systemverilog we have '(mylogic) to automatically cast at the right size. Is there anything similar?