Here is my GCD.scala

package gcd

import chisel3._

class GCD extends Module {
  val io = IO(new Bundle {
    val value1        = Input(UInt(16.W))
    val value2        = Input(UInt(16.W))
    val loadingValues = Input(Bool())
    val outputGCD     = Output(UInt(16.W))
    val outputValid   = Output(Bool())
  })

  val x = Reg(UInt())
  val y = Reg(UInt())

  when(x > y) { x := x - y }.otherwise { y := y - x }

  when(io.loadingValues) {
    x := io.value1
    y := io.value2
  }

  io.outputGCD   := x
  io.outputValid := y === 0.U
}

object Elaborate extends App {
  val firtoolOptions = Array("--lowering-options=" + List(
    "disallowLocalVariables",
    "disallowPackedArrays",
    "locationInfoStyle=wrapInAtSquareBracket"
  ).reduce(_ + "," + _))
  circt.stage.ChiselStage.emitSystemVerilogFile(new gcd.GCD(), args, firtoolOptions)
}

I’m using Chisel 6.4.0:

ivy"org.chipsalliance::chisel:6.4.0"
ivy"org.chipsalliance:::chisel-plugin:6.4.0"
ivy"edu.berkeley.cs::chiseltest:6.0.0"

It seems Chisel 6 will emit systemverilog by default.

When I switch to Chisel 3, getVerilogString() is useful to generate verilog, but it will also generate systemverilog from Chisel 6.4.0.

I’ve searched for lots of solutions, they all solved based on Chisel 3.

How can I generate verilog from Chisel 6.4.0 ?