So I have been stuck for days on this problem i have been messing around with the applications of a direct digital synthesizer (to see background info on look at this link).to see the LPM megafunction look at this link.
my question is when i have the following code :

MyMux:lpm_MUX
        GENERIC MAP
        (
            LPM_WIDTH=>1,
            LPM_SIZE=>8,
            LPM_WIDTHS=>1
        )
        PORT MAP
        (
            data(0,7 to 0)=>singal_test,
            data(1,7 to 0)=>in_Mux,
            sel=>out_DFF2(0),
            result=>dataout
        );

so when i try this code in the dds architecture i get the following error
Error (10486): VHDL error at DSS.vhd(108): slice of object cannot be specified for an object that has an array type of more than one dimension
I have also been thinking if this doesn’t work, I will make a mux from scratch. The only problem is I plan singal_test which is a test to be connected to the first entry of my lut is this a case of having to generate that address where 0 is and get the output of the lut? does anyone know a better way of doing this. As you see I am a bit lost in what i can do to fix this problem