This is the piece of Makefile I’m referring to:

$(API1): $(OBJDIR)/$(API1)/$(API1_FILES).o
    @mkdir -p $(APISDIR)
    @$(CXX) $(CXXFLAGS) $(OBJDIR)/$@/*.o -o $(APISDIR)/$@
    @printf "$(_SUCCESS) $(GREEN)- $@ maked!n$(RESET)"

$(API2): $(OBJDIR)/$(API2)/$(API2_FILES).o
    @mkdir -p $(APISDIR)
    @$(CXX) $(CXXFLAGS) $(OBJDIR)/$@/*.o -o $(APISDIR)/$@
    @printf "$(_SUCCESS) $(GREEN)- $@ maked!n$(RESET)"

$(API3): $(OBJDIR)/$(API3)/$(API3_FILES).o
    @mkdir -p $(APISDIR)
    @$(CXX) $(CXXFLAGS) $(OBJDIR)/$@/*.o -o $(APISDIR)/$@
    @printf "$(_SUCCESS) $(GREEN)- $@ maked!n$(RESET)"

...

in which the variables API1, API2, API3 are the names of apis that I want to compile autonomously, and API1_FILES, … API3_FILES are the names of the files (without .cpp extenision) needed for each api, including one main() function for each file list.
Everything is working fine, but I really wanted to collapse some of this, especially because the recipes are the same for each api.

Are there some obscure methods, like a variable loop for recipes or something? Or any other way to recover the current recipe name (as with $@)?

I made new varialbes

APIS         = $(API1) $(API2) $(API3) #...
APIS_FILES   = $(API1_FILES) $(API2_FILES) $(API3_FILES) #...

and tried something like

$(APIS): $(OBJDIR)/$@/$(APIS_FILES).o
    @mkdir -p $(APISDIR)
    @$(CXX) $(CXXFLAGS) $(OBJDIR)/$@/*.o -o $(APISDIR)/$@
    @printf "$(_SUCCESS) $(GREEN)- $@ maked!n$(RESET)"

that would be working for each api, were only automatic variables expanded in the prerequisites line, which aren’t.
I am not worried about the compilation of all files from API_FILES, since I can simply check the existence of the .cpp file in the source folder.