Good morning,

I have tried to do it in different ways. In the first case reducing the logic of the module for the control of the index value etc, verilator told me that it is not a constant value and I agree with that and then I change for the second version but I got the same result. Do you know how I can describe this logic in SystemVerilog?

1º:

module m1 (
input  logic [4:0] in1,  // 8-bit input vector 1
input  logic [4:0] in2,  // 8-bit index
output logic [4:0] out   // 8-bit output vector
);
logic add;

always_comb begin
add = (in2[in1[4:0]-1] & (in2[(in1[4:0]-2):0] != '0); //summary rounding
end

out = in1 + add;//summary of the final operation
endmodule

2º

module m1 (
input  logic [4:0] in1,  // 8-bit input vector 1
input  logic [4:0] in2,  // 8-bit index
output logic [4:0] out   // 8-bit output vector
);
logic add;

always_comb begin
for (int i = 0; i < 4; i++) begin
if((in1[4:0]-2) == i)begin
add = (in2[in1[4:0]-1] & (in2[(i:0] != '0); //summary rounding
end
end

out = in1 + add;//summary of the final operation
endmodule

The logic I am trying to implement its the rounding mode of riscv-v 1.0.

Any ideas on how I can approach this logic?

I have tried several tests trying to do static logic but I can’t find a way to solve the problem.
I would like to know how I can implement this logic in hardware.