i use i an j in module to perform addition and multiplication. but i want to increment both in the way that their value automatically change within the modules for addition and multiplication

module V1_2D_CAT(
    input logic [7:0] block[31:0][31:0], // Input block of data
    input logic [19:0] kd,               // Input parameter kd
    output logic [13:0] in_out,          // Output signal in_out
    input logic clk,                     // Clock signal
    output logic [25:0] jn_out           // Output signal jn_out
);

    // Internal signals
    logic [4:0] ud, vd, rid, rjd;
    logic [4:0] i = 0, j = 0;
    logic [6:0] z1;
    logic [9:0] z2_intermed_product;
    logic [11:0] z2;
    logic [9:0] z3_intermed_product;
    logic [11:0] z3;
    logic [9:0] in_intermed_1_product;
    logic [11:0] in_intermed_1_add1;
    logic [13:0] in;
    logic [23:0] jn_intermed;
    logic [25:0] jn;

    // Component Instantiations
    fix_add #(.N(5)) add1_inst (
        .addend1({{{1'b0}}, rid}),
        .addend2({{{1'b0}}, rjd}),
        .sum(z1)
    );

    fix_mult #(.INPUT_WIDTH(5), .OUTPUT_WIDTH(10)) mult1_inst (
        .multiplicand(vd),
        .multiplier(ud),
        .result(z2_intermed_product)
    );

    fix_add #(.N(10)) add2_inst (
        .addend1({{{1'b0}}, z2_intermed_product}),
        .addend2(11'b00000000001),
        .sum(z2)
    );

    fix_mult #(.INPUT_WIDTH(5), .OUTPUT_WIDTH(10)) mult2_inst (
        .multiplicand(i),
        .multiplier(vd),
        .result(z3_intermed_product)
    );

    fix_add #(.N(10)) add3_inst (
        .addend1({{{1'b0}}, z3_intermed_product}),
        .addend2({{6{1'b0}}, rjd}),
        .sum(z3)
    );

    fix_mult #(.INPUT_WIDTH(5), .OUTPUT_WIDTH(10)) mult3_inst (
        .multiplicand(vd),
        .multiplier(j),
        .result(in_intermed_1_product)
    );

    fix_add #(.N(10)) add4_inst (
        .addend1({{{1'b0}}, in_intermed_1_product}),
        .addend2({{6{1'b0}}, i}),
        .sum(in_intermed_1_add1)
    );

    fix_add #(.N(12)) add5_inst (
        .addend1({{{1'b0}}, in_intermed_1_add1}),
        .addend2({{6{1'b0}}, z1}),
        .sum(in)
    );

    fix_mult #(.INPUT_WIDTH(12), .OUTPUT_WIDTH(24)) mult4_inst (
        .multiplicand(z2),
        .multiplier({{7{1'b0}}, j}),
        .result(jn_intermed)
    );

    fix_add #(.N(24)) add6_inst (
        .addend1({{{1'b0}}, jn_intermed}),
        .addend2({{13{1'b0}}, z3}),
        .sum(jn)
    );

    // Output assignments
    assign jn_out = jn;
    assign in_out = in;

    // Clock-driven block for iterating over the block indices
    always @(posedge clk) begin
        if (i < 31) begin
            if (j < 31) begin
                j <= j + 1;
            end else begin
                j <= 0;
                i <= i + 1;
            end
        end else begin
            i <= 0; // Reset i at the end of the iteration
        end
    end

    // Initial assignments of signals, can be modified as per requirements
    initial begin
        ud = 5'b10101;  // Example value, replace with kd[19:15]
        rid = 5'b01010; // Example value, replace with kd[14:10]
        rjd = 5'b00111; // Example value, replace with kd[9:5]
        vd = 5'b11001;  // Example value, replace with kd[4:0]
    end

endmodule

i tried to use wire définition for i an j but it doesn’t change my result, i and j stay both at 0 in modules regardless the increment in the always block