I have this component that is supposed to control the temperature of an oven, increasing or decreasing the temperature value, how can I install this same component and pass this signal to the Fpga?

‘ve been trying to put 4 bits in one heX, and 4 in the other, but the representation is all wrong, letters like F,A,C appear… and it doesn’t count as I want, in fact I have no idea how to do that

the component code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ControloTemperatura IS
GENERIC (temp_amb : NATURAL := 20);
PORT (
clk : IN STD_LOGIC;
clk_en_1HZ : IN STD_LOGIC;
resist : IN STD_LOGIC;
reset : IN STD_LOGIC;
Temperatura : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ControloTemperatura;

ARCHITECTURE Behavioral OF ControloTemperatura IS
SIGNAL s_temp, s_temp_amb : unsigned (7 DOWNTO 0);
SIGNAL s_cnt_time : unsigned (3 DOWNTO 0);
BEGIN
s_temp_amb <= to_unsigned(temp_amb, 8);

PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF reset = '1' THEN
s_temp <= s_temp_amb;
s_cnt_time <= (OTHERS => '0');
ELSIF clk_en_1HZ = '1' THEN
IF s_cnt_time = 5 THEN
s_cnt_time <= (OTHERS => '0');
IF resist = '0' THEN
IF s_temp <= s_temp_amb THEN
s_temp <= s_temp_amb;
ELSE
s_temp <= s_temp - 1;
END IF;
ELSE
s_temp <= s_temp + 1;
END IF;
ELSE
s_cnt_time <= s_cnt_time + 1;
END IF;
END IF;
END IF;
END PROCESS;
Temperatura <= std_logic_vector(s_temp);
END Behavioral;

as I have been trying to do:

    clk_div_4hz : ENTITY work.ClkDividerN(RTL)
        GENERIC MAP(k => 50000000)

    s_temp_units_decod : ENTITY work.Bin7SegDecoder(RTL)
        PORT MAP(
            enable => '1',
            binInput => temperatura_signal(3 DOWNTO 0), 
            decOut_n => HEX2 
        );

    s_temp_tens_decod : ENTITY work.Bin7SegDecoder(RTL)
        PORT MAP(
            enable => '1',
            binInput => temperatura_signal(7 DOWNTO 4), 
            decOut_n => HEX3 
        );