I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in “a_s” and odd ones in “b_s” and this 16 inputs at a time (8 in a and 8 in b).
Each 16 inputs are loaded and used in calculations in the “BFU_SET” for each FSM cycle using indexes calculated from a counter “state_num”.
The issue is that in the simulation the odd values of “state_num” are bypassed and the calculations i want are done only on the even values.
in the code below w_in_s, a_in_s, b_in_s are example values
the entity gives correct results for the calculated values in the even indexes
BFU_VALID checks if the calculation is finished before registering
the small states between 2 BFU_VALIDs are ITERATE for the loading of inputs and calculations and REG is for saving the results.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_STAGE.all;
entity STAGE_v2 is
port (
--a : in std_logic_vector(128*11-1 downto 0)
--b : in std_logic_vector(128*11-1 downto 0)
--w : in std_logic_vector(128*11-1 downto 0)
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
--u_out, v_out : out std_logic_vector(128*11-1 downto 0);
--y_out : out std_logic_vector(256*12-1 downto 0);
valid_out : out std_logic
);
end entity;
architecture rtl of STAGE_v2 is
signal w_in_s : arr_128_12 := ("000000000001", "000000000001", "000000000001", "000000000001", "000000000001", ...);
signal a_in_s : arr_128_12 := ("010101010010", "000101000111", "001011110011", "100111100011", "001001111010", ...);
signal b_in_s : arr_128_12 := ("011001101010", "011110100011", "011010111100", "010000111111", "001110001101"...); -- to input the inputs from tb
signal u_out_s, v_out_s : arr_128_12;
type arr_8_12 is array (0 to 7) of std_logic_vector(11 downto 0);
signal a_s, b_s : arr_8_12; -- to manage the inouts of the bfu set
signal u_s, v_s : arr_8_12;
signal w_s : arr_8_12;
type state_type is (IDLE, ITERATE, BFU_VALID, REG, CONCAT, DONE);
signal state, next_state : state_type;
signal valid_bfu_set, start_bfu_set : std_logic;
signal state_num : integer := 0;
signal y_s : arr_256_12;
signal y_out_reg, y_out : std_logic_vector(256*12-1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
state <= IDLE;
valid_out <= '0';
y_s <= (others => (others => '0'));
y_out <= (others => '0');
y_out_reg <= (others => '0');
state_num <= 0;
start_bfu_set <= '0';
elsif rising_edge(clk) then
state <= next_state;
case state is
when IDLE =>
start_bfu_set <= '0';
if start = 'U' then
next_state <= ITERATE;
else
next_state <= IDLE;
end if;
valid_out <= '0';
when ITERATE =>
start_bfu_set <= '1';
a_s <= (a_in_s(state_num*8),a_in_s(state_num*8+1),a_in_s(state_num*8+2),a_in_s(state_num*8+3),a_in_s(state_num*8+4),a_in_s(state_num*8+5),a_in_s(state_num*8+6),a_in_s(state_num*8+7));
b_s <= (b_in_s(state_num*8),b_in_s(state_num*8+1),b_in_s(state_num*8+2),b_in_s(state_num*8+3),b_in_s(state_num*8+4),b_in_s(state_num*8+5),b_in_s(state_num*8+6),b_in_s(state_num*8+7));
w_s <= (w_in_s(state_num*8),w_in_s(state_num*8+1),w_in_s(state_num*8+2),w_in_s(state_num*8+3),w_in_s(state_num*8+4),w_in_s(state_num*8+5),w_in_s(state_num*8+6),w_in_s(state_num*8+7));
next_state <= BFU_VALID;
when BFU_VALID =>
start_bfu_set <= '0';
if valid_bfu_set = '1' then
next_state <= REG;
else
next_state <= BFU_VALID;
end if;
when REG =>
start_bfu_set <= '0';
y_s(state_num*16) <= u_s(0);
y_s(state_num*16+1) <= v_s(0);
y_s(state_num*16+2) <= u_s(1);
y_s(state_num*16+3) <= v_s(1);
y_s(state_num*16+4) <= u_s(2);
y_s(state_num*16+5) <= v_s(2);
y_s(state_num*16+6) <= u_s(3);
y_s(state_num*16+7) <= v_s(3);
y_s(state_num*16+8) <= u_s(4);
y_s(state_num*16+9) <= v_s(4);
y_s(state_num*16+10) <= u_s(5);
y_s(state_num*16+11) <= v_s(5);
y_s(state_num*16+12) <= u_s(6);
y_s(state_num*16+13) <= v_s(6);
y_s(state_num*16+14) <= u_s(7);
y_s(state_num*16+15) <= v_s(7);
if state_num >= 15 then
next_state <= CONCAT;
else
state_num <= state_num + 1;
next_state <= ITERATE;
end if;
when CONCAT =>
start_bfu_set <= '0';
y_out_reg <= concat_stdlv_arr_256_12(y_s);
state_num <= 0;
next_state <= DONE;
when DONE =>
start_bfu_set <= '0';
y_out <= y_out_reg;
next_state <= IDLE;
valid_out <= '1';
when others =>
next_state <= IDLE;
end case;
end if;
end process;
ct_bfu_set_8_inst: entity work.CT_BFU_SET_8
port map (
clk => clk,
reset => reset,
start => start_bfu_set,
a0 => a_s(0),
a1 => a_s(1),
a2 => a_s(2),
a3 => a_s(3),
a4 => a_s(4),
a5 => a_s(5),
a6 => a_s(6),
a7 => a_s(7),
b0 => b_s(0),
b1 => b_s(1),
b2 => b_s(2),
b3 => b_s(3),
b4 => b_s(4),
b5 => b_s(5),
b6 => b_s(6),
b7 => b_s(7),
w0 => w_s(0),
w1 => w_s(1),
w2 => w_s(2),
w3 => w_s(3),
w4 => w_s(4),
w5 => w_s(5),
w6 => w_s(6),
w7 => w_s(7),
u_out0 => u_s(0),
u_out1 => u_s(1),
u_out2 => u_s(2),
u_out3 => u_s(3),
u_out4 => u_s(4),
u_out5 => u_s(5),
u_out6 => u_s(6),
u_out7 => u_s(7),
v_out0 => v_s(0),
v_out1 => v_s(1),
v_out2 => v_s(2),
v_out3 => v_s(3),
v_out4 => v_s(4),
v_out5 => v_s(5),
v_out6 => v_s(6),
v_out7 => v_s(7),
valid_out => valid_bfu_set
);
end architecture;
What i tried:
First i was verifying the “end of calculations” to go register in the ITERATE state then i made it a state by itself “BDU_VALID”, it did not work, i also mover the counter’s incrementation “state_num <= state_num + 1” through different places out side or inside the condition and in different states.
New contributor
Anis Bensidhoum is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.