I am using Vivado 2017, trying to work with XADC. This is the block design I am using:block_design_XADC
But I get this duplicated interconnect warning when I try to synthesize the sign after creating the HDL_wrapper:
duplicate warning
When I ignore the warning and try to create the bitstream, it fails again. I don’t know if they are related. But I have no duplicated modules or IPs in my block design. What is actually causing this duplicate warning and how can I resolve it?
I tried to synthesize the design and then check the IO ports but I get this duplicate design warning.
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