I was looking at the Cortex-M55 TRM document and came across the following statement:

‘Normal shareable cacheable attributes are converted to Normal Shareable Noncacheable by the processor’ (arm_cortex_m55_processor_trm_101051_0101_03_en.pdf, page 183).

Does this mean that on the Cortex-M55, it is not possible to set attributes as both shareable and cacheable?

What I tried:

I reviewed the Cortex-M55 Technical Reference Manual (TRM), specifically looking at the section on memory attributes and cache behaviors. I focused on the statement regarding the conversion of normal shareable cacheable attributes to normal shareable noncacheable.

What I was expecting:

I expected to find clarification on whether the Cortex-M55 processor supports memory attributes that are both shareable and cacheable simultaneously. My goal was to understand if the processor imposes any restrictions on setting memory regions to be both shareable and cacheable.