We have a DMA design with FIFO stream input.

We let FIFO accumulate the entirety of data stream i.e 0x8001 depth and width is 32 bit.

Then we cut off the Input stream to FIFO since it is external.

And then we request 4 Bytes Read from PS, While the FIFO write count is steady at 0x8001.

But after we receive 4Bytes in PS, when we check the FIFO wr count, it has decreased from 0x8001 to 0x7FC7.

The data left in FIFO is less than what was expected.

I.e., 0x8001 – 0x7FC7 = 3A (d58). If we exclude the 4 byte which was read i.e., 1 memory location , Then we are missing almost 57 * 4 = 228 Bytes !

Is this related to burst size ?

What could be causing this ?