I’m having trouble understanding the difference between or the use of instantiating components instead of directly using an array or std_logic_vector().
for example if im designing a register file with 32 registers and each register has a size of 32 bits, should i be instantiating 32 D Flip-Flops for the register and mapping the input of the flip-flops to the input of the register and then instantiate 32 registers for the register file and map inputs of the registers to the input of the register file?
Or have an array to represent the registers in a register file?
<code>type t_registers is array (0 to 31) of std_logic_vector(31 downto 0);
signal registers: t_registers;
</code>
<code>type t_registers is array (0 to 31) of std_logic_vector(31 downto 0);
signal registers: t_registers;
</code>
type t_registers is array (0 to 31) of std_logic_vector(31 downto 0);
signal registers: t_registers;
Which method should I be using in general when im writing VHDL? Should I worry about the internal components of each entity? How is the array represented in hardware?