I created an simple flipflop instance and testbench, with VHDL.
Besides I wanted to use the property assertions in systemverilog for degugging. Despite the sva errors work correctly, being report at the correct time, I would like to know how to debug this property assertions. And also why what I see, is in the wave signals and inputs in the .sv files, present always a value of X.

How can this be possible when the signals coming from the VHDL show the correct value?

I present the code I use, the commands to compile, simulate and the screenshot of the wave.

d_flipflop.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_flipflop is
    Port (
        d : in  STD_LOGIC;
        clk : in  STD_LOGIC;
    rst_n : in  STD_LOGIC; -- Active low reset
    q : out STD_LOGIC
    );
end D_flipflop;

architecture Behavioral of D_flipflop is
begin
    process (CLK, rst_n) 
    begin
    if (rst_n = '0') then
        Q <= '0'; -- Reset the output to 0
        elsif rising_edge(CLK) then
        Q <= D; -- Transfer the input D to output Q on clock's rising edge 
    end if;
    end process;
end Behavioral;

assertion_tb.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;

entity tb is
end tb;

architecture Behavioral of tb is
    signal clk   : STD_LOGIC := '0';
    signal rst_n : STD_LOGIC := '0';
    signal d     : STD_LOGIC := '0';
    signal q1    : STD_LOGIC;
    signal q2    : STD_LOGIC;
    signal primera_seed : positive;
    signal segunda_seed : positive;

    -- Procedure for generating random number (0 or 1)
    procedure generate_random_signal(signal primera_seed, segunda_seed : inout positive; signal sig : out STD_LOGIC) is
        variable rand  : real;
        variable seed1 : positive := primera_seed;
        variable seed2 : positive := segunda_seed;
    begin
        
        uniform(seed1, seed2, rand);
        if rand <= 0.5 then
            sig <= '0';
        else
            sig <= '1';
            end if;
            primera_seed <= seed1;
            segunda_seed <= seed2;
    end procedure;

begin
    -- Instantiate D_flipflop components
    dff1: entity work.D_flipflop
    port map (
        clk   => clk,
        rst_n => rst_n,
        d     => d,
        q     => q1
    );
    dff2: entity work.D_flipflop
    port map (
        clk   => clk,
        rst_n => rst_n,
        d     => d,
        q     => q2
    );
    
    -- Clock generation
    clk_process : process
    begin
        while True loop
            clk <= not clk;
            wait for 2 ns;
        end loop;
    end process;
    
    -- Stimulus process
    stim_process : process
    begin
        rst_n <= '0';
        d <= '0';
        wait for 3 ns;
        rst_n <= '1';
        for i in 0 to 5 loop
            generate_random_signal(primera_seed, segunda_seed, d);
            wait for 3 ns;
            generate_random_signal(primera_seed, segunda_seed, rst_n);
        end loop;
    wait for 10 ns;
    std.env.stop;
    end process;
    
    -- Monitor process
    monitor_process : process
    begin
        while True loop
        wait for 1 ns;
        report "At time = " & time'image(now) & ": rst_n = " & std_logic'image(rst_n) & ", d = " & std_logic'image(d) & ", q1 = " & std_logic'image(q1) & ", q2 = " & std_logic'image(q2);
        end loop;
    end process;
end Behavioral;

assertion.sv

module assertion_dff (
    input clk, rst_n, d
);
    logic q;
    sequence seq1;
    d ##1 q;
    endsequence 
  
    property prop;
    @(posedge clk) disable iff(rst_n)
    d |=> seq1;
    endproperty
  
    dff_assert: assert property (prop) else $display("Assertion failed at time = %0t", $time);
endmodule

assertion_wrapper.sv

module assertion_dff_wrapper (
input clk,
input rst_n,
input d,
input q
);
  
bind tb.dff2 assertion_dff single_inst(.clk(clk),
.rst_n(rst_n),
.d(d),
.q(q));
  
endmodule