Modeling a D-type Flip Flop in Verilog with gate-level modeling vs. behavioral modeling seems to result in state transitions happening at different edges of the clock signal. I’m sure I’m missing something, so looking for some guidance. With a gate-level model, there are two internal D Latches (at least the way I’m doing it) with the second (output) latch having an inverted clock signal. On the positive edge, the first latch picks up the input, and on the negative edge the second latch propagates the input to the output. With a behavioral model (triggering on posedge) the output of the latch seems to transition instantly on the positive edge. These seem to be two very different outcomes. This is when doing simulation via iverilog or Vivado.

The CPU works fine with either behavioral or gate-level modeling, but the transitions happen on different phases of the clock signal.

Behavioral, transitions happen on positive edge

reg [15:0] R;
assign OUT = R;

initial R = 0;
always@(posedge CLK) begin
    if(ST) begin
        R <= X;
    end
end

Behavioral Schematic

Gate-Level, transitions happen on the negative edge

Gate-Level Schematic

If I update the behavioral Verilog to trigger on the negative edge, my application (a CPU) fails.

Question is: does this matter? Is there a better way to do a behavioral model of a D-type flip flop that more closely matches a gate-level implementation? Or, if you do simulation after synthesis does this difference go away? Thanks in advance!