I was trying to code a D-Flip Flop with active-low asynchronous reset with NAND-gates.
Below, is the schematic for the same.
Verilog Codes for 2-input nand gate & 3-input nand-gate:
<code>module nand2
( input i0,
input i1,
output z
);
assign z = ~(i0 & i1);
endmodule
module nand3
( input i0,
input i1,
input i2,
output z
);
assign z = ~(i0 & i1 & i2);
endmodule
</code>
<code>module nand2
( input i0,
input i1,
output z
);
assign z = ~(i0 & i1);
endmodule
module nand3
( input i0,
input i1,
input i2,
output z
);
assign z = ~(i0 & i1 & i2);
endmodule
</code>
module nand2
( input i0,
input i1,
output z
);
assign z = ~(i0 & i1);
endmodule
module nand3
( input i0,
input i1,
input i2,
output z
);
assign z = ~(i0 & i1 & i2);
endmodule
Verilog Code for DFF:
<code>module DFF
( input CK,
input RD,
input D,
output Q,
output QN
);
wire net_nand21_in0_nand33_out;
wire net_nand31_in0_nand21_out;
wire net_nand22_in0_nand31_out;
wire net_nand34_in1_nand32_out;
nand2 NAND21(.i0(net_nand21_in0_nand33_out), .i1(net_nand22_in0_nand31_out), .z(net_nand31_in0_nand21_out));
nand3 NAND31(.i0(net_nand31_in0_nand21_out), .i1(CK), .i2(RD), .z(net_nand22_in0_nand31_out));
nand3 NAND32(.i0(net_nand22_in0_nand31_out), .i1(CK), .i2(net_nand21_in0_nand33_out), .z(net_nand34_in1_nand32_out));
nand3 NAND33(.i0(net_nand34_in1_nand32_out), .i1(RD), .i2(D), .z(net_nand21_in0_nand33_out));
nand2 NAND22(.i0(net_nand22_in0_nand31_out), .i1(QN), .z(Q));
nand3 NAND34(.i0(Q), .i1(net_nand34_in1_nand32_out), .i2(RD), .z(QN));
endmodule
</code>
<code>module DFF
( input CK,
input RD,
input D,
output Q,
output QN
);
wire net_nand21_in0_nand33_out;
wire net_nand31_in0_nand21_out;
wire net_nand22_in0_nand31_out;
wire net_nand34_in1_nand32_out;
nand2 NAND21(.i0(net_nand21_in0_nand33_out), .i1(net_nand22_in0_nand31_out), .z(net_nand31_in0_nand21_out));
nand3 NAND31(.i0(net_nand31_in0_nand21_out), .i1(CK), .i2(RD), .z(net_nand22_in0_nand31_out));
nand3 NAND32(.i0(net_nand22_in0_nand31_out), .i1(CK), .i2(net_nand21_in0_nand33_out), .z(net_nand34_in1_nand32_out));
nand3 NAND33(.i0(net_nand34_in1_nand32_out), .i1(RD), .i2(D), .z(net_nand21_in0_nand33_out));
nand2 NAND22(.i0(net_nand22_in0_nand31_out), .i1(QN), .z(Q));
nand3 NAND34(.i0(Q), .i1(net_nand34_in1_nand32_out), .i2(RD), .z(QN));
endmodule
</code>
module DFF
( input CK,
input RD,
input D,
output Q,
output QN
);
wire net_nand21_in0_nand33_out;
wire net_nand31_in0_nand21_out;
wire net_nand22_in0_nand31_out;
wire net_nand34_in1_nand32_out;
nand2 NAND21(.i0(net_nand21_in0_nand33_out), .i1(net_nand22_in0_nand31_out), .z(net_nand31_in0_nand21_out));
nand3 NAND31(.i0(net_nand31_in0_nand21_out), .i1(CK), .i2(RD), .z(net_nand22_in0_nand31_out));
nand3 NAND32(.i0(net_nand22_in0_nand31_out), .i1(CK), .i2(net_nand21_in0_nand33_out), .z(net_nand34_in1_nand32_out));
nand3 NAND33(.i0(net_nand34_in1_nand32_out), .i1(RD), .i2(D), .z(net_nand21_in0_nand33_out));
nand2 NAND22(.i0(net_nand22_in0_nand31_out), .i1(QN), .z(Q));
nand3 NAND34(.i0(Q), .i1(net_nand34_in1_nand32_out), .i2(RD), .z(QN));
endmodule
Testbench of the DFF:
<code>module DFF_tb();
reg D;
reg CK;
reg RD;
wire Q;
wire QN;
DFF dut(D,CK,RD,Q,QN);
initial begin
CK=0;
forever #10 CK = ~CK;
end
initial begin
RD=0;
D <= 1;
#50;
RD=1;
#50;
D <= 0;
#50;
D <= 1;
end
endmodule
</code>
<code>module DFF_tb();
reg D;
reg CK;
reg RD;
wire Q;
wire QN;
DFF dut(D,CK,RD,Q,QN);
initial begin
CK=0;
forever #10 CK = ~CK;
end
initial begin
RD=0;
D <= 1;
#50;
RD=1;
#50;
D <= 0;
#50;
D <= 1;
end
endmodule
</code>
module DFF_tb();
reg D;
reg CK;
reg RD;
wire Q;
wire QN;
DFF dut(D,CK,RD,Q,QN);
initial begin
CK=0;
forever #10 CK = ~CK;
end
initial begin
RD=0;
D <= 1;
#50;
RD=1;
#50;
D <= 0;
#50;
D <= 1;
end
endmodule
The waveforms are still not behaving as a D-FlipFlop with active-low async-reset:
Can you please help me with the problem? Is there some issue with the schematic or with the code?
Thanks & Regards,
Parth.