I’ve been trying to compile a “.v” file into a “.vvp” file but, when i code and run in terminal, i doesn’t run. Here the module code, test bench code and the terminal code:

//modulo and_gate

module and_gate (input A, input B, output Y);
    assign Y = A & B;
endmodule

//Testbench do modulo and_gate
`include "and_gate.v"
module and_gate_tb;
    reg A;
    reg B;
    wire Y;

    // Instancia o módulo and_gate
    and_gate uut (
        .A(A),
        .B(B),
        .Y(Y)
    );

    initial begin
        // Simulação de diferentes casos de teste
        A = 0; B = 0; #10;
        A = 0; B = 1; #10;
        A = 1; B = 0; #10;
        A = 1; B = 1; #10;
        $stop; // Para a simulação
    end
endmodule

PS C:iverilogbinTestews-verilogProjeto1> iverilog -o and_gate_tb.vvp and_gate_tb.v

I already checked the directory, the instalation of icarus verilog and the Path of iverilogbin

I’ve already tried to reinstal the iverilog, reinstal the extensions, coded many times and nothing changes. I would like some help (And other detail is in the vsCode terminal it doesn’t say what was the error.