I have this set and reset test bench:

module sr_tb;
        reg s = 0;
        reg r = 0;

        wire p;
        wire q;
        wire y;

        or or1(y, s, p);
        not not1(q, r);
        and and1(p, y, q);

        initial
//              $monitor("s:%h, r:%h, p:%h, q:%h | %t",
//      s, r, p, q, $time);
//
                $monitor("s:%h, r:%h, y:%h",
                        s, r, y);

        initial begin
                #1 s = 1;
                #1 s = 0;
                #1 r = 1;
                #1 r = 0;
                #1 $finish;
        end


endmodule

Here is the monitor log:

~/verilog $ iverilog -o sr_tb sr_tb.v && ./sr_tb
s:0, r:0, y:x
s:1, r:0, y:1
s:0, r:0, y:1
s:0, r:1, y:0
s:0, r:0, y:0
sr_tb.v:25: $finish called at 5 (1s)

As you see, there is undefined state (x) in the monitor log, how do I convert it to high impedance state (z) so that it will act as bidirectional pin.