I’m a beginner in FPGA programming and I’m trying to implement a noise filter in Verilog on Vivado. I want to operate at 100 kHz and I’m doing that by doing my calculations every 1024 clock cycles with a 125 MHz clock. For this, I have a counter and a counter1024 that resets every 1024 cycles. When I synthesize my design, I get an error “[Synth 8-6858] multi-driven net Q[31] is connected to at least one constant driver which has been preserved, other driver is ignored” which I guess is due to defining something wrong, but I can’t figure out what the problem is because logically it should be updating correctly and the line that gives an error is not a line I added. Does anyone have any suggestions on how I could fix this error?

Here is the code that I’m using:

    reg [31:0]          counter=0, counter_next=0, counter1024=0, counter1024_next=0;   
    reg [31:0]          counter_output=0, counter_output_next=0;
    reg [31:0]          cycle=0, cycle_next=0;
    reg [1:0]           counter_eq_1024;

// Handling of counter, counter_output and cycle buffer
    always @(posedge clk) 
    begin
        if (~rst) 
        begin
            counter <= 0;
            counter_output <= 0;
            **counter1024 <= 0;**
            cycle <= 0;
        end
        **else if (counter1024 == 1024) begin
            counter_eq_1024 = 1'b1;
            counter1024 = 1'b0;
            counter1024_next = 1'b0;     
        end** else
        begin
            counter <= counter_next;
            **counter1024 <= counter1024_next;**
            counter_output <= counter_output_next;
            cycle <= cycle_next;
            **counter_eq_1024 <= 1'b0;**
        end
        
    end


    always @* // logic for counter, counter_output, and cycle buffer
    begin
        counter_next = counter + 1; // increment on each clock cycle
        **counter1024_next = counter1024 + 1;**
        counter_output_next = counter_output;
        cycle_next = cycle;
        
        if (state < state_next) // high to low signal transition
        begin
            cycle_next = cycle + 1; // increment on each signal transition
            if (cycle >= Ncycles-1) 
            begin
                counter_next = 0;
                **counter1024_next = 0;**
                counter_output_next = counter;
                cycle_next = 0;
            end
        end
   end

For context, I’m modifying one of Anton Potočnik’s projects and the lines that are my addition are marked in bold. Here is also the full version of the code.(The error message)