I’m trying to index into a 2D array in Verilog like this:

`include "src/elementwise_multiplication.v"

module parallel_elementwise_multiplication_dynamic #(parameter N = 8, parameter M = 2) (
    input wire [N-1:0] a [0:M-1][0:N-1],
    input wire [N-1:0] b [0:M-1][0:N-1],
    output wire [2*N-1:0] result [0:M-1][0:N-1]
    );

    genvar i;
    generate
        // Instantiate elementwise_multiplication modules for each pair of arrays
        for (i = 0; i < M; i = i + 1) begin : instantiate_multiplication
            elementwise_multiplication #(N) inst (
                .a(a[i]),
                .b(b[i]),
                .result(result[i])
            );
        end
    endgenerate
endmodule

However, I get this error in iverilog:

src/parallel_elementwise_multiplication_dynamic.v:14: 
sorry: Array slices are not yet supported for continuous assignment.

Im expecting the code to synthesize, so that i will be able to have dynamic generation of elementwise_multiplication modules.