I am trying to understand the ARM cortex-M hardware behavior on reset; particularly how the SP and PC values are written upon a cold start or hard reset.

Basically, it would seem the hardware (aka PE or Processing Element as referred to by the Arm v7 Architecture Reference Manual) is doing this somehow. The first word of the vector table at 0x0 is taken for SP initialization and the next word gives the address of the reset vector which is loaded to the PC, and a branch to that address is performed to run whatever the reset vector does to continue the booting process. However I’m curious ‘how’ this is actually being done by the hardware.

From the Arm v7-M Architecture Ref Manual, Section “B1.5.5 Reset Behavior” describes actions taken upon reset through a pseudocode (truncated here just to focus on the actions specific to the question):

// TakeReset()
// ============
TakeReset()
   ..
   ..
   ..
   bits(32) vectortable = VTOR<31:7>:'0000000';
   SP_main = MemA_with_priv[vectortable, 4, AccType_VECTABLE] AND 0xFFFFFFFC<31:0>;
   SP_process = ((bits(30) UNKNOWN):'00');
   LR = 0xFFFFFFFF<31:0>; /* preset to an illegal exception return value */
   tmp = MemA_with_priv[vectortable+4, 4, AccType_VECTABLE];
   ...
   ...
   BranchTo(tmp AND 0xFFFFFFFE<31:0>); /* address of reset service routine */

Ignoring the rest of the actions (setting all registers to their reset defaults etc.) how are the actions of setting SP_main and the BranchTo() to reset service routine actually performed? I know this may be ‘implementation defined’ but how might they be implemented:

1. Are they hardcoded instructions somewhere in the on-chip ROM area so that the PC upon reset has the address of the instruction to read address 0x0 and load the SP and then load the PC and jump to the reset routine? (In addition to rest of the actions given in the TakeReset() pseudocode)
2. Is there hardwired logic to do these two initial steps such that these steps are being done before the processor begins it’s fetch and execute phase. It would seem more efficient for the reset state of the core to be tied to the appropriate instructions, rather than implementing additional logic to perform these actions.

P.S.
A quick search here did find a few similar questions that provide some answers, but didn’t find one that specifically answers the question asked here..
ARM Cortex-m4 boot sequence
What is the booting process for ARM?
On reset what happens in embedded system?
Where to find the intended boot sequence of an MCU