I am developing a custom RTL block on a AMD Versal platform. This block reads data from a specific location in DDR memory provided by the Processing System (PS) through the RTL’s slave interface. The data is then processed, and the processed data is written back to a different location in DDR memory. The RTL utilizes an AXI Full Master interface to perform both reading and writing operations with the DDR memory.

However, I am encountering an issue where neither reading nor writing operations are occurring between the RTL and DDR.

Here’s what I’ve done so far:

• Processing Logic: Designed and validated the processing logic.
• Slave Interface: Added and validated an AXI Lite slave interface to the RTL logic. This interface allows the PS to control registers
  within the RTL.
• Master Interface: Added an AXI Full Master interface and connected it to the S06_AXI port of the AXI NoC. Mapped S06_AXI to MC port 3 in the AXI NoC and assigned proper addresses (C3_DDR_LOW0 and C3_DDR_LOW1) to S06_AXI, which is connected to MC port 3. (Since the PS also connects to DDR, I verified that the addresses the RTL Master
  reads from or writes to are accessible.)
• Default AXI Master Code: To isolate the issue from my custom Master interface code, I used the default AXI Master code generated
  by Vivado (“Create and Package New IP > Create AXI Peripheral”). I’m
  driving the Master’s INIT_AXI_TXN signal using the RTL’s slave
  interface and monitoring the TXN_DONE and ERROR signals from the
  Master interface using the slave interface.
• Observation: The TXN_DONE signal consistently remains at 0, indicating that transactions are never completing successfully.

Below is the block design that I’m using.

Can some one please help me find the issue?

Thank you in advance.