Waveform picture
Why is the value of a = 1 but y = 0 at 35ns? What is the difference between always begin #delay block and always #delay begin block?
module tb;
reg y;
reg a;
//$monitor("time = %t, a = %d", $time, a);
always begin
#5 a = ~a;
end
initial begin
a = 0;
#50; $finish;
end
always #7 begin
y = a;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, tb);
end
endmodule
1
I’ve tested using Icarus Verilog 10.3 two files, which differ in the block:
always #7 begin
y = a;
end
and
always begin
#7 y = a;
end
The iverilog vvp outputs for both files differ only in the internal IDs. So the resulting waveforms does not differ.
The y value at 35ns is the previous a value (at previous tick). This’s the expected behavior.
1
You have a Verilog simulation race condition in your code. You are trying to assign y to the value of a at the time a changes at time 35ns. The simulator is not guaranteed to assign 0 or 1 to y. It can choose either value and be compliant with the IEEE Std 1800-2023. The simulator chooses to assign 0.
Your code does not adhere to recommended coding practices. When you don’t use good coding practices, you can end up with simulation results that you don’t understand.