Current Configuration and Flow:

UART Configuration:

UART is in FIFO mode with a buffer size of 64 bytes.
Tx/Rx interrupts are configured as edge-triggered.
Data Reception:

The application receives 64 bytes of data over UART every 20 milliseconds.
FIFO watermark is set to 40 bytes.
First interrupt (FIFO_WATERMARK) triggers an ISR to copy received bytes to a local buffer.
Second interrupt handles the RX_LAST bytes in the FIFO.
Observed Issue:

Random Interrupt Failure:

After power on, the first UART interrupt triggers and the ISR executes.
Subsequent interrupts do not occur.
This issue is observed randomly, approximately 1 in every 100 power cycles.
Pending Status:

The GIC’s Pending status register shows the UART interrupt as pending.
The pending status does not clear even after handling the interrupt in the ISR.

What can be potential cause of this issue? Is there any limitation from edge trigger interrupt? Is there a possibility that this issue can arise because second interrupt getting triggred before the first interrupts ISR execution is still in progress? If the second interrupt is triggered before the first interrupt’s ISR has completed, it could lead to a race condition. This might cause the interrupt state machine to get stuck, especially if the ISR does not handle nested interrupts properly?