Why does x always block get triggered only two times and y always block get triggered 3 times? The waveform after running the code is “x” is 1 at time = 7ns and stays high, for “y” its 1 at time = 7ns and then 0 at time = 9ns giving a square pulse like “a”

module tb;
reg x, y;
reg a;

initial begin 
  a = 0; 
  #5 a = 1;
  #2 a = 0;
  #200; 
  $finish; 
end

  
  always @(a) begin
   $display("x always block triggered - value of a = %0b", a); 
   x = #2 a;
  end
  
  always @(a) begin
   $display("y always block triggered - value of a = %0b", a); 
   y <= #2 a;
  end
  
  
initial begin
  $dumpfile("dump.vcd");
  $dumpvars(0, tb);
end
endmodule

I was expecting both always blocks to be triggered three times…when a = 0, rising edge of “a” at 5ns and falling edge of “a” at 7ns. Can someone point me to what topics I need to learn in Verilog to know this.