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Question

I can use general perf commands like perf record or perf report, but when I type perf c2c record -a ./my_program in terminal, it shows failed: memory events not supported.

Please help resolve this problem.

The list below includes information I can think of. If anything is missing, please let me know.

C:WindowsSystem32>wsl –update

Newest windows subsystem Linux installed

C:WindowsSystem32>wsl –version

WSL Version: 2.2.4.0

Kernel Version: 5.15.153.1-2

WSLg Version: 1.0.61

MSRDC Version: 1.2.5326

Direct3D Version: 1.611.1-81528511

DXCore Version: 10.0.26091.1-240325-1447.ge-release

Windows Version: 10.0.22631.3880

C:WindowsSystem32>wsl –list –verbose

NAME STATE VERSION

Ubuntu Running 2

linux-environment@DESKTOP-VC5TFK0:~/queue$ uname -r

5.15.153.1-microsoft-standard-WSL2

linux-environment@DESKTOP-VC5TFK0:~/queue$ zcat /proc/config.gz | grep PERF

CONFIG_CGROUP_PERF=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# CONFIG_PERF_EVENTS_INTEL_UNCORE is not set
# CONFIG_PERF_EVENTS_INTEL_RAPL is not set
# CONFIG_PERF_EVENTS_INTEL_CSTATE is not set
# CONFIG_PERF_EVENTS_AMD_POWER is not set
# CONFIG_PERF_EVENTS_AMD_UNCORE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_CLS_U32_PERF=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set

liscpu:

Architecture:                       x86_64
CPU op-mode(s):                     32-bit, 64-bit
Address sizes:                      48 bits physical, 48 bits virtual
Byte Order:                         Little Endian
CPU(s):                             6
On-line CPU(s) list:                0-5
Vendor ID:                          AuthenticAMD
Model name:                         AMD Ryzen 5 4500U with Radeon Graphics
CPU family:                         23
Model:                              96
Thread(s) per core:                 1
Core(s) per socket:                 6
Socket(s):                          1
Stepping:                           1
BogoMIPS:                           4740.97
Flags:                              fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl tsc_reliable nonstop_tsc cpuid extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw topoext perfctr_core ssbd ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 clzero xsaveerptr arat npt nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold v_vmsave_vmload umip rdpid
Virtualization:                     AMD-V
Hypervisor vendor:                  Microsoft
Virtualization type:                full
L1d cache:                          192 KiB (6 instances)
L1i cache:                          192 KiB (6 instances)
L2 cache:                           3 MiB (6 instances)
L3 cache:                           4 MiB (1 instance)

linux-environment@DESKTOP-VC5TFK0:~/queue$ perf list | grep -E ‘mem_load_retired|cache’

  cache-misses                                       [Hardware event]
  cache-references                                   [Hardware event]
  L1-dcache-load-misses                              [Hardware cache event]
  L1-dcache-loads                                    [Hardware cache event]
  L1-dcache-prefetches                               [Hardware cache event]
  L1-icache-load-misses                              [Hardware cache event]
  L1-icache-loads                                    [Hardware cache event]
  branch-load-misses                                 [Hardware cache event]
  branch-loads                                       [Hardware cache event]
  dTLB-load-misses                                   [Hardware cache event]
  dTLB-loads                                         [Hardware cache event]
  iTLB-load-misses                                   [Hardware cache event]
  iTLB-loads                                         [Hardware cache event]
  cache-misses OR cpu/cache-misses/                  [Kernel PMU event]
  cache-references OR cpu/cache-references/          [Kernel PMU event]
cache:
  ic_cache_fill_l2                                  
       [The number of 64 byte instruction cache line was fulfilled from the L2
        cache]
  ic_cache_fill_sys                                 
       [The number of 64 byte instruction cache line fulfilled from system
        memory or another cache]
  ic_cache_inval.fill_invalidated                   
        instruction cache lines invalidated. A non-SMC event is CMC (cross
  ic_cache_inval.l2_invalidating_probe              
        number of instruction cache lines invalidated. A non-SMC event is CMC
        instruction decoder (includes non-cacheable and cacheable fill
  l2_cache_req_stat.ic_access_in_l2                 
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Instruction cache requests in L2]
  l2_cache_req_stat.ic_dc_hit_in_l2                 
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Instruction cache request hit in L2 and Data cache request
  l2_cache_req_stat.ic_dc_miss_in_l2                
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Instruction cache request miss in L2 and Data cache request
  l2_cache_req_stat.ic_fill_hit_s                   
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Instruction cache hit clean line in L2]
  l2_cache_req_stat.ic_fill_hit_x                   
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Instruction cache hit modifiable line in L2]
  l2_cache_req_stat.ic_fill_miss                    
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Instruction cache request miss in L2]
  l2_cache_req_stat.ls_rd_blk_c                     
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Data cache request miss in L2 (all types)]
  l2_cache_req_stat.ls_rd_blk_cs                    
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Data cache shared read hit in L2]
  l2_cache_req_stat.ls_rd_blk_l_hit_s               
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Data cache read hit on shared line in L2]
  l2_cache_req_stat.ls_rd_blk_l_hit_x               
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Data cache read hit in L2]
  l2_cache_req_stat.ls_rd_blk_x                     
       [Core to L2 cacheable request access status (not including L2
        Prefetch). Data cache store or state change hit in L2]
       [L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead]
        pipeline which miss the L2 cache and hit the L3]
        pipeline which miss the L2 and the L3 caches]
  l2_request_g1.cacheable_ic_read                   
       [All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads]
       [All L2 Cache Requests (Breakdown 1 - Common). Data cache state change
       [All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads]
       [All L2 Cache Requests (Breakdown 1 - Common). Data cache reads
       [All L2 Cache Requests (Breakdown 1 - Common). Data cache stores]
       [All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read
       [All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read
        sized non-cacheable]
       [All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized]
       [All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized
        non-cacheable]
       [LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2
        WCB (Write Combining Buffer) cache line zeroing requests]
       [Number of accesses to the dcache for load/store references]
  ls_hw_pf_dc_fill.ls_mabresp_lcl_cache             
       [Hardware Prefetch Data Cache Fills by Data Source. From another cache
  ls_hw_pf_dc_fill.ls_mabresp_rmt_cache             
       [Hardware Prefetch Data Cache Fills by Data Source. From another cache
        cache boundary or is done on an uncacheable memory type. Comparable to
       [Retired lock instructions. High speculative cacheable lock speculation
       [Retired lock instructions. Low speculative cacheable lock speculation
  ls_refills_from_sys.ls_mabresp_lcl_cache          
       [Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not
  ls_refills_from_sys.ls_mabresp_rmt_cache          
       [Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and
       [A non-cacheable store and the non-cacheable commit buffer is full]
  ls_sw_pf_dc_fill.ls_mabresp_lcl_cache             
       [Software Prefetch Data Cache Fills by Data Source. From another cache
  ls_sw_pf_dc_fill.ls_mabresp_rmt_cache             
       [Software Prefetch Data Cache Fills by Data Source. From another cache
  de_dis_uops_from_decoder.opcache_dispatched       
  l2_cache_accesses_from_dc_misses                  
  l2_cache_accesses_from_ic_misses                  
  l2_cache_hits_from_dc_misses                      
  l2_cache_hits_from_ic_misses                      
  l2_cache_hits_from_l2_hwpf                        
  l2_cache_misses_from_dc_misses                    
  l2_cache_misses_from_ic_miss                      
  sdt_libc:memory_tcache_double_free                 [SDT event]
  sdt_libc:memory_tunable_tcache_count               [SDT event]
  sdt_libc:memory_tunable_tcache_max_bytes           [SDT event]
  sdt_libc:memory_tunable_tcache_unsorted_limit      [SDT event]
l2_cache:
  all_l2_cache_accesses
  all_l2_cache_hits
  all_l2_cache_misses
  l2_cache_accesses_from_l2_hwpf
  l2_cache_misses_from_l2_hwpf
l3_cache:

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Danh mục

cannot run perf c2c under WSL2 environment