I’m currently trying to generate an algorithmically calculated signal using a zybo zynq z010 board and Vitis. I fill a Look Up Table with this signal in a for loop and then send this Look Up Table to a Pmod using another for loop. I’d like to use the 1 GB of DDR3 memory on the FPGA board to store my LUT, but I don’t know how to access it.

My problem is that I need a very large Look Up Table (10 million 16-bit values) and if I implement a Look Up table of more than 7000 values my code crashes. The BRAM Blocks on Vivado have a too small memory for my problem.