I have this vhdl code and as you can see, I’m trying to write it synthesizable and it’s gonna be like a ram that tries to first read from the input and then when the mode is 1, it tries to make the output as same as the input 1024 clock earlier. I’ve also wrote a test bench for it and ran the simulator but the output is all ‘U’ and memory doesn’t get changed either.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity VHDL4 is
    Port ( Input : in  STD_LOGIC_VECTOR(7 downto 0);
              RST : in STD_LOGIC;
           Mode : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Output : out  STD_LOGIC_VECTOR(7 downto 0));
end VHDL4;

architecture Behavioral of VHDL4 is
    SIGNAL counter:INTEGER:=0;
    SIGNAL memory:STD_LOGIC_VECTOR(8192 downto 0):=(others => '0');
begin
    PROCESS(CLK)
    BEGIN
        if CLK = '1' and CLK'event then
            if RST = '1' then
                counter <= 0;
            else
                counter <= (counter + 1) mod 1024;
            end if;
        end if;
    END PROCESS;
    
    PROCESS(CLK)
    BEGIN
        if CLK = '1' and CLK'event then
            if RST = '0' then
                if Mode = '0' then
                    memory(((counter * 8) + 7) downto (counter*8)) <= Input;
                else
                    Output <= memory(((counter*8) + 7) downto (counter*8));
                end if;
            end if;
        end if;
    END PROCESS;
end Behavioral;

I don’t know what the problem is but I think it’s because the memory signal doesn’t get driven.