I want to automatically generate targets for many modules. The Makefile works if the files are in the same folder. I would like to make it work for different paths.

relevant part of the Makefile:

MODULE_NAMES = exact_adder_1bit exact_multiplier_2bit
MODULE_PATHS = adder/exact_adder_1bit/ multiplier/

define MODULE_TEMPLATE

$(1)_tb.vcd: $(1)
    vvp $$<

$(1).vvp:
    iverilog -o $(1) $(1)_tb.v $(1).v
    vvp $(1)

sim_$(1):
    iverilog -o $(1) $(1)_tb.v $(1).v
    vvp $(1)

endef

$(foreach MODULE_NAME,$(MODULE_NAMES),$(eval $(call MODULE_TEMPLATE,$(MODULE_NAME))))

My idea would be to iterate through 2 lists, but it does not work:

$(foreach MODULE_NAME,MODULE_PATH,$(MODULE_NAMES),$(MODULE_PATHS),$(eval $(call MODULE_TEMPLATE,$(MODULE_NAME),$(MODULE_PATH))))

Then I could access it with $(1) and $(2).