I’m a beginner in FPGA programming and I’m trying to implement a noise filter in Verilog on Vivado. Right now my project failed timing due to negative slack (WNS=-15ns). I’m trying to run around 100 kHz by doing calculations every 1024 clock cycles with a 125 MHz clock (code below). I understand that my calculations take too long for a clock cycle, and it’s specifically the x_next calculation at the moment that is taking the longest time. I cannot pipeline my calculations any more because all variables are dependent on the previous one, so they need to be evaluated sequentially. I thought about setting a multicycle path but I’m not that advanced yet in FPGA programming so I’m not sure if I can do it. Does anyone have any other suggestions on how I can make my calculations run faster?

Here is my code:

    reg [31:0] y, y_init, u; 
    reg [31:0] x_curr, x_curr0, x_curr1, x_curr2, x_next, x_next2, x_next3;
    reg [31:0] e_pre_var, e_next_var, e_next_var1, e_next_var2;
    reg [31:0] K_pre, K_next, one_K_next_sq, K_next_sq; // kalman gain
      
     
    always@(posedge clk) begin
    
        if (counter == 0) begin
                y_init = y_measured;
                x_next2 = k_omega*y_init;
                x_next3 = oT*x_next2;
                x_next = x_next1 - x_next3; // predict the next state x_n
                e_pre_var = e_pre_var0; // make sure this is a positive number   
        end
            
        if (counter_eq_1024) begin             
             
            y = y_measured;
            u = -oT*k_omega*y;
            
            K_next_num = (phi_sq*e_pre_var + d_var);
            K_next_denom = (phi_sq*e_pre_var + d_var + s_var);
//            K_next = K_next_num / K_next_denom;
            M_AXIS_OUT_tvalid_kal = 1'b1; // send the numerator and denominator values to the                  Divider Generator
            K_next = K_next_in; // get the kalman gain result from the Divider Generator
        
            x_curr0 = 1-K_next;
            x_curr1 = x_curr0*x_next;
            x_curr2 = K_next*y;
            x_curr = x_curr1 + x_curr2; // estimate the current state
            
            x_next = phi*x_curr + u; // predict the next state
            
            //e_next_var = (1-K_next)*(1-K_next)*(phi*phi*e_pre_var + d_var) + K_next*K_next*s_var;
            one_K_next_sq = (1-K_next)*(1-K_next);
            K_next_sq = K_next*K_next;
            e_next_var1 = one_K_next_sq*K_next_num;
            e_next_var2 = K_next_sq*s_var;
            e_next_var = e_next_var1 + e_next_var2;
            
            // make the next values the old values for next cycle
            K_pre = K_next;
            e_pre_var = e_next_var;
     
            
            // Assign the calculated value to the output signal
            M_AXIS_OUT_tdata = x_next;
            
            // Store sampled data in memory
            x_data = x_next;
            
            M_AXIS_OUT_tvalid_kal = 1'b0; // stop data flow to Divider Generator
        end
    end

All other values not declared as reg are parameters. Here is also the full code of which I’m modifying one of Anton Potočnik’s projects. Here is also a screenshot of the worst critical path.