I’m trying to build a clock divider based on integer counters. the simulation works correctly but the synthesis fails with the error above and marks line 25.
I don’t understand the reason why it isn’t synthesizable. Thank you for your help.

the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity divider is
  Port (clk_100M: in std_logic;
        reset: in std_logic;
        clk_5, clk_500: buffer std_logic := '0' );
end divider;

architecture Behavioral of divider is
begin

CLK_GEN:
process(clk_100M)
variable count_5: integer:=0;
variable count_500: integer:=0;
begin    
    if rising_edge(reset) then
        clk_5 <= '0';
        clk_500 <= '0'; 
        count_5 := 0;
        count_500 := 0;
    elsif rising_edge(clk_100M) then
        count_5 := count_5 + 1;
        count_500 := count_500 + 1;
    end if;
    
    if count_5 = 5000000 then
        clk_5 <= NOT(clk_5);
        count_5 := 0;
    end if;
         
    if count_500 = 50000 then
        clk_500 <= NOT(clk_500);
        count_500 := 0;    
    end if;
        
end process;

end Behavioral;