I want to make a 16-bit multiplier. The way it works is that I take two 32-bit numbers from the input and multiply them with the least valuable 16 bits and give them to the output, and I also use a 32-bit adder. In every clock, the multiplier shifts right and the multiplicand shifts left, and after 16 clocks, the output is ready, but the output is always zero.
Of course, the 32-bit adder works correctly.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 

entity multi_32bit is
    Port ( Start : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           A : in  STD_LOGIC_VECTOR (31 downto 0);
           B : in  STD_LOGIC_VECTOR (31 downto 0);
           Y : out  STD_LOGIC_VECTOR (31 downto 0);
           Ready : out  STD_LOGIC);
end multi_32bit;

architecture Behavioral of multi_32bit is

    component Full_Adder_32bit is
        Port ( A : in  STD_LOGIC_VECTOR (31 downto 0); 
               B : in  STD_LOGIC_VECTOR (31 downto 0);
               Cin : in  STD_LOGIC;
               S : out  STD_LOGIC_VECTOR (31 downto 0);
               Cout : out  STD_LOGIC);
    end component;

    signal product : std_logic_vector (31 downto 0) := (others => '0');
    signal product_temp : std_logic_vector (31 downto 0);
     signal miltiplier : std_logic_vector (31 downto 0) := "0000000000000000" & A(15 downto 0);
     signal miltiplicand : std_logic_vector (15 downto 0) := B(15 downto 0);
    signal shift_A : std_logic_vector (31 downto 0) := miltiplier;
    signal shift_B : std_logic_vector (15 downto 0) := miltiplicand;
    signal c : std_logic;
    signal count : integer range 0 to 16 := 0;

begin
    FA: component Full_Adder_32bit port map(product,shift_A,'0',product_temp,c );

    process(CLK)
    begin
        if rising_edge(CLK) then
            if Start = '1' then
                if shift_B(0) = '1' then
                    product <= std_logic_vector(unsigned(product) + unsigned(shift_A));
                          --product <= product + product_temp;
                else
                    product <= product; 
                end if;
                shift_B <= '0' & shift_B(15 downto 1);
                shift_A <=  shift_A(30 downto 0) & '0';
                    count <= count + 1;`your text`
                if count = 16 then
                    Ready <= '1';
                    Y <= product;  
                end if;
            else
                product <= (others => '0'); 
                     Ready <= '0';
            end if;
        end if;
    end process;
     Y <= product;
end Behavioral;

The output is 0 after 16 clock, but Ready is 1. Of course, in the test bench, every time I set the start to 0 and then 1, this time, ready is not 1 even after 16 clock. Only the first test bench after 16 clock ready will be 1 and after that it will be 0 again