If we have a watchpoint that is hit when a write operation happens to a particular address.

What could cause a delay between issuing the write operation and triggering the watchpoint.

I guess the watchpoint is triggered at the decode stage of the pipeline. Does it mean that if the pipeline is flushed before the write operation, it might be delayed?

Is the watchpoint actually hit at the write issue time or at the actual write to memory.

I am interested in how this implemented on ARM Cortex M cores.