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Question

I’ve installed yosys. I’ve installed the systemverilog plugin from https://github.com/chipsalliance/synlig.

I can load the plugin, but then it can’t find the top module.

yosys -p "plugin -i systemverilog" -p "read_systemverilog src/main.sv; synth_gowin -top top -json synthesis.json"

 /----------------------------------------------------------------------------
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <[email protected]>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 ----------------------------------------------------------------------------/
 Yosys 0.40 (git sha1 a1bb0255d65, clang++ 15.0.0 -fPIC -Os)

-- Running command `plugin -i systemverilog' --

-- Running command `read_systemverilog src/main.sv; synth_gowin -top top -json synthesis.json' --
    -noassert
        ignore assert() statements
    -debug
        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2

    -dump_ast1
        dump abstract syntax tree (before simplification)

    -dump_ast2
        dump abstract syntax tree (after simplification)

    -no_dump_ptr
        do not include hex memory addresses in dump (easier to diff dumps)

    -dump_vlog1
        dump ast as Verilog code (before simplification)

    -dump_vlog2
        dump ast as Verilog code (after simplification)

    -dump_rtlil
        dump generated RTLIL netlist

    -defer
        only read the abstract syntax tree and defer actual compilation
        to a later 'hierarchy' command. Useful in cases where the default
        parameters of modules yield invalid or not synthesizable code.
        Needs to be followed by read_systemverilog -link after reading
        all files.

    -link
        performs linking and elaboration of the files read with -defer

    -parse-only
        this parameter only applies to read_systemverilog command,
        it runs only Surelog to parse design, but doesn't load generated
        tree into Yosys.

    -formal
        enable support for SystemVerilog assertions and some Yosys extensions
        replace the implicit -D SYNTHESIS with -D FORMAL

1. Executing SYNTH_GOWIN pass.

1.1. Executing Verilog-2005 frontend: /Users/justinzaun/local/brew/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/Users/justinzaun/local/brew/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `LUT1'.
Generating RTLIL representation for module `LUT2'.
Generating RTLIL representation for module `LUT3'.
Generating RTLIL representation for module `LUT4'.
Generating RTLIL representation for module `__APICULA_LUT5'.
Generating RTLIL representation for module `__APICULA_LUT6'.
Generating RTLIL representation for module `__APICULA_LUT7'.
Generating RTLIL representation for module `__APICULA_LUT8'.
Generating RTLIL representation for module `MUX2'.
Generating RTLIL representation for module `MUX2_LUT5'.
Generating RTLIL representation for module `MUX2_LUT6'.
Generating RTLIL representation for module `MUX2_LUT7'.
Generating RTLIL representation for module `MUX2_LUT8'.
Generating RTLIL representation for module `DFF'.
Generating RTLIL representation for module `DFFE'.
Generating RTLIL representation for module `DFFS'.
Generating RTLIL representation for module `DFFSE'.
Generating RTLIL representation for module `DFFR'.
Generating RTLIL representation for module `DFFRE'.
Generating RTLIL representation for module `DFFP'.
Generating RTLIL representation for module `DFFPE'.
Generating RTLIL representation for module `DFFC'.
Generating RTLIL representation for module `DFFCE'.
Generating RTLIL representation for module `DFFN'.
Generating RTLIL representation for module `DFFNE'.
Generating RTLIL representation for module `DFFNS'.
Generating RTLIL representation for module `DFFNSE'.
Generating RTLIL representation for module `DFFNR'.
Generating RTLIL representation for module `DFFNRE'.
Generating RTLIL representation for module `DFFNP'.
Generating RTLIL representation for module `DFFNPE'.
Generating RTLIL representation for module `DFFNC'.
Generating RTLIL representation for module `DFFNCE'.
Generating RTLIL representation for module `VCC'.
Generating RTLIL representation for module `GND'.
Generating RTLIL representation for module `IBUF'.
Generating RTLIL representation for module `OBUF'.
Generating RTLIL representation for module `TBUF'.
Generating RTLIL representation for module `IOBUF'.
Generating RTLIL representation for module `ELVDS_OBUF'.
Generating RTLIL representation for module `TLVDS_OBUF'.
Generating RTLIL representation for module `OSER4'.
Generating RTLIL representation for module `OSER8'.
Generating RTLIL representation for module `OSER10'.
Generating RTLIL representation for module `OVIDEO'.
Generating RTLIL representation for module `OSER16'.
Generating RTLIL representation for module `IDES4'.
Generating RTLIL representation for module `IDES8'.
Generating RTLIL representation for module `IDES10'.
Generating RTLIL representation for module `IVIDEO'.
Generating RTLIL representation for module `IDES16'.
Generating RTLIL representation for module `IDDR'.
Generating RTLIL representation for module `IDDRC'.
Generating RTLIL representation for module `ODDR'.
Generating RTLIL representation for module `ODDRC'.
Generating RTLIL representation for module `GSR'.
Generating RTLIL representation for module `ALU'.
Generating RTLIL representation for module `RAM16S1'.
Generating RTLIL representation for module `RAM16S2'.
Generating RTLIL representation for module `RAM16S4'.
Generating RTLIL representation for module `RAM16SDP1'.
Generating RTLIL representation for module `RAM16SDP2'.
Generating RTLIL representation for module `RAM16SDP4'.
Generating RTLIL representation for module `SP'.
Generating RTLIL representation for module `SPX9'.
Generating RTLIL representation for module `SDP'.
Generating RTLIL representation for module `SDPX9'.
Generating RTLIL representation for module `DP'.
Generating RTLIL representation for module `DPX9'.
Generating RTLIL representation for module `rPLL'.
Generating RTLIL representation for module `PLLVR'.
Generating RTLIL representation for module `OSC'.
Generating RTLIL representation for module `OSCZ'.
Generating RTLIL representation for module `OSCF'.
Generating RTLIL representation for module `OSCH'.
Generating RTLIL representation for module `OSCW'.
Generating RTLIL representation for module `OSCO'.
Successfully finished Verilog frontend.

1.2. Executing Verilog-2005 frontend: /Users/justinzaun/local/brew/bin/../share/yosys/gowin/cells_xtra.v
Parsing Verilog input from `/Users/justinzaun/local/brew/bin/../share/yosys/gowin/cells_xtra.v' to AST representation.
Generating RTLIL representation for module `MUX2_MUX8'.
Generating RTLIL representation for module `MUX2_MUX16'.
Generating RTLIL representation for module `MUX2_MUX32'.
Generating RTLIL representation for module `MUX4'.
Generating RTLIL representation for module `MUX8'.
Generating RTLIL representation for module `MUX16'.
Generating RTLIL representation for module `MUX32'.
Generating RTLIL representation for module `LUT5'.
Generating RTLIL representation for module `LUT6'.
Generating RTLIL representation for module `LUT7'.
Generating RTLIL representation for module `LUT8'.
Generating RTLIL representation for module `DL'.
Generating RTLIL representation for module `DLE'.
Generating RTLIL representation for module `DLC'.
Generating RTLIL representation for module `DLCE'.
Generating RTLIL representation for module `DLP'.
Generating RTLIL representation for module `DLPE'.
Generating RTLIL representation for module `DLN'.
Generating RTLIL representation for module `DLNE'.
Generating RTLIL representation for module `DLNC'.
Generating RTLIL representation for module `DLNCE'.
Generating RTLIL representation for module `DLNP'.
Generating RTLIL representation for module `DLNPE'.
Generating RTLIL representation for module `INV'.
Generating RTLIL representation for module `IODELAY'.
Generating RTLIL representation for module `IEM'.
Generating RTLIL representation for module `ROM16'.
Generating RTLIL representation for module `ROM'.
Generating RTLIL representation for module `ROMX9'.
Generating RTLIL representation for module `rSDP'.
Generating RTLIL representation for module `rSDPX9'.
Generating RTLIL representation for module `rROM'.
Generating RTLIL representation for module `rROMX9'.
Generating RTLIL representation for module `pROM'.
Generating RTLIL representation for module `pROMX9'.
Generating RTLIL representation for module `SDPB'.
Generating RTLIL representation for module `SDPX9B'.
Generating RTLIL representation for module `DPB'.
Generating RTLIL representation for module `DPX9B'.
Generating RTLIL representation for module `PADD18'.
Generating RTLIL representation for module `PADD9'.
Generating RTLIL representation for module `MULT9X9'.
Generating RTLIL representation for module `MULT18X18'.
Generating RTLIL representation for module `MULT36X36'.
Generating RTLIL representation for module `MULTALU36X18'.
Generating RTLIL representation for module `MULTADDALU18X18'.
Generating RTLIL representation for module `MULTALU18X18'.
Generating RTLIL representation for module `ALU54D'.
Generating RTLIL representation for module `BUFG'.
Generating RTLIL representation for module `BUFS'.
Generating RTLIL representation for module `PLL'.
Generating RTLIL representation for module `TLVDS_IBUF'.
Generating RTLIL representation for module `TLVDS_TBUF'.
Generating RTLIL representation for module `TLVDS_IOBUF'.
Generating RTLIL representation for module `ELVDS_IBUF'.
Generating RTLIL representation for module `ELVDS_TBUF'.
Generating RTLIL representation for module `ELVDS_IOBUF'.
Generating RTLIL representation for module `MIPI_IBUF'.
Generating RTLIL representation for module `MIPI_IBUF_HS'.
Generating RTLIL representation for module `MIPI_IBUF_LP'.
Generating RTLIL representation for module `MIPI_OBUF'.
Generating RTLIL representation for module `MIPI_OBUF_A'.
Generating RTLIL representation for module `I3C_IOBUF'.
Generating RTLIL representation for module `CLKDIV'.
Generating RTLIL representation for module `DHCEN'.
Generating RTLIL representation for module `DLL'.
Generating RTLIL representation for module `DLLDLY'.
Generating RTLIL representation for module `FLASH96K'.
Generating RTLIL representation for module `FLASH256K'.
Generating RTLIL representation for module `FLASH608K'.
Generating RTLIL representation for module `DCS'.
Generating RTLIL representation for module `DQCE'.
Generating RTLIL representation for module `FLASH128K'.
Generating RTLIL representation for module `MCU'.
Generating RTLIL representation for module `USB20_PHY'.
Generating RTLIL representation for module `ADC'.
Generating RTLIL representation for module `BANDGAP'.
Generating RTLIL representation for module `CLKDIV2'.
Generating RTLIL representation for module `DCC'.
Generating RTLIL representation for module `DHCENC'.
Generating RTLIL representation for module `EMCU'.
Generating RTLIL representation for module `FLASH64K'.
Generating RTLIL representation for module `FLASH64KZ'.
Generating RTLIL representation for module `I3C'.
Generating RTLIL representation for module `IODELAYA'.
Generating RTLIL representation for module `IODELAYC'.
Generating RTLIL representation for module `SPMI'.
Generating RTLIL representation for module `IODELAYB'.
Generating RTLIL representation for module `PLLO'.
Generating RTLIL representation for module `DCCG'.
Generating RTLIL representation for module `FLASH96KA'.
Generating RTLIL representation for module `MIPI_DPHY_RX'.
Generating RTLIL representation for module `CLKDIVG'.
Successfully finished Verilog frontend.

1.3. Executing HIERARCHY pass (managing design hierarchy).
ERROR: Module `top' not found!

all that is in src/main.sv is a simple top module to count on some leds:

module top
(
  input CLK,
  output [5:0] LED
);

reg [23:0] wait_counter = 'd0;
reg [5:0] ledCounter = 0;

assign LED = ~ledCounter;

always @(posedge CLK) begin
  if (wait_counter < 13500000) begin
    wait_counter <= wait_counter + 'd1;
  end
  else begin
    wait_counter <= 'd0;
    ledCounter <= ledCounter + 'd1;
  end
end

endmodule

This same code WILL build with just Verilog, but I’m trying to get it to build as SystemVerilog as I want to start using SystemVerilog features.

yosys -p "read_verilog src/main.sv; synth_gowin -top top -json synthesis.json"   

 /----------------------------------------------------------------------------
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <[email protected]>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 ----------------------------------------------------------------------------/
 Yosys 0.40 (git sha1 a1bb0255d65, clang++ 15.0.0 -fPIC -Os)

-- Running command `read_verilog src/main.sv; synth_gowin -top top -json synthesis.json' --

1. Executing Verilog-2005 frontend: src/main.sv
Parsing Verilog input from `src/main.sv' to AST representation.
Generating RTLIL representation for module `top'.
Successfully finished Verilog frontend.

2. Executing SYNTH_GOWIN pass.

2.1. Executing Verilog-2005 frontend: /Users/justinzaun/local/brew/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/Users/justinzaun/local/brew/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `LUT1'.
Generating RTLIL representation for module `LUT2'.
Generating RTLIL representation for module `LUT3'.
Generating RTLIL representation for module `LUT4'.
Generating RTLIL representation for module `__APICULA_LUT5'.
Generating RTLIL representation for module `__APICULA_LUT6'.
Generating RTLIL representation for module `__APICULA_LUT7'.
Generating RTLIL representation for module `__APICULA_LUT8'.
Generating RTLIL representation for module `MUX2'.
Generating RTLIL representation for module `MUX2_LUT5'.
Generating RTLIL representation for module `MUX2_LUT6'.
Generating RTLIL representation for module `MUX2_LUT7'.
Generating RTLIL representation for module `MUX2_LUT8'.
Generating RTLIL representation for module `DFF'.
Generating RTLIL representation for module `DFFE'.
Generating RTLIL representation for module `DFFS'.
Generating RTLIL representation for module `DFFSE'.
Generating RTLIL representation for module `DFFR'.
Generating RTLIL representation for module `DFFRE'.
Generating RTLIL representation for module `DFFP'.
Generating RTLIL representation for module `DFFPE'.
Generating RTLIL representation for module `DFFC'.
Generating RTLIL representation for module `DFFCE'.
Generating RTLIL representation for module `DFFN'.
Generating RTLIL representation for module `DFFNE'.
Generating RTLIL representation for module `DFFNS'.
Generating RTLIL representation for module `DFFNSE'.
Generating RTLIL representation for module `DFFNR'.
Generating RTLIL representation for module `DFFNRE'.
Generating RTLIL representation for module `DFFNP'.
Generating RTLIL representation for module `DFFNPE'.
Generating RTLIL representation for module `DFFNC'.
Generating RTLIL representation for module `DFFNCE'.
Generating RTLIL representation for module `VCC'.
Generating RTLIL representation for module `GND'.
Generating RTLIL representation for module `IBUF'.
Generating RTLIL representation for module `OBUF'.
Generating RTLIL representation for module `TBUF'.
Generating RTLIL representation for module `IOBUF'.
Generating RTLIL representation for module `ELVDS_OBUF'.
Generating RTLIL representation for module `TLVDS_OBUF'.
Generating RTLIL representation for module `OSER4'.
Generating RTLIL representation for module `OSER8'.
Generating RTLIL representation for module `OSER10'.
Generating RTLIL representation for module `OVIDEO'.
Generating RTLIL representation for module `OSER16'.
Generating RTLIL representation for module `IDES4'.
Generating RTLIL representation for module `IDES8'.
Generating RTLIL representation for module `IDES10'.
Generating RTLIL representation for module `IVIDEO'.
Generating RTLIL representation for module `IDES16'.
Generating RTLIL representation for module `IDDR'.
Generating RTLIL representation for module `IDDRC'.
Generating RTLIL representation for module `ODDR'.
Generating RTLIL representation for module `ODDRC'.
Generating RTLIL representation for module `GSR'.
Generating RTLIL representation for module `ALU'.
Generating RTLIL representation for module `RAM16S1'.
Generating RTLIL representation for module `RAM16S2'.
Generating RTLIL representation for module `RAM16S4'.
Generating RTLIL representation for module `RAM16SDP1'.
Generating RTLIL representation for module `RAM16SDP2'.
Generating RTLIL representation for module `RAM16SDP4'.
Generating RTLIL representation for module `SP'.
Generating RTLIL representation for module `SPX9'.
Generating RTLIL representation for module `SDP'.
Generating RTLIL representation for module `SDPX9'.
Generating RTLIL representation for module `DP'.
Generating RTLIL representation for module `DPX9'.
Generating RTLIL representation for module `rPLL'.
Generating RTLIL representation for module `PLLVR'.
Generating RTLIL representation for module `OSC'.
Generating RTLIL representation for module `OSCZ'.
Generating RTLIL representation for module `OSCF'.
Generating RTLIL representation for module `OSCH'.
Generating RTLIL representation for module `OSCW'.
Generating RTLIL representation for module `OSCO'.
Successfully finished Verilog frontend.

*** REMOVED A BUNCH OF LOGS ***

2.30. Printing statistics.

=== top ===

   Number of wires:                130
   Number of wire bits:            177
   Number of public wires:         130
   Number of public wire bits:     177
   Number of ports:                  2
   Number of port bits:              7
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                114
     ALU                            54
     DFFE                            6
     DFFR                           24
     GND                             1
     IBUF                            1
     LUT1                           12
     LUT2                            1
     LUT4                            3
     MUX2_LUT5                       4
     MUX2_LUT6                       1
     OBUF                            6
     VCC                             1

2.31. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

2.32. Executing JSON backend.

End of script. Logfile hash: 691ee5878c, CPU: user 0.22s system 0.01s
Yosys 0.40 (git sha1 a1bb0255d65, clang++ 15.0.0 -fPIC -Os)
Time spent: 28% 20x read_verilog (0 sec), 11% 1x abc9_exe (0 sec), ...

What am I doing wrong?

Thiết kế website giá rẻ

Danh mục

yosys works with Verilog but not with SystemVerilog (with the systemverilog plugin)