In CPU data path there are blocks called data memory and instruction memory. Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally L1 and L2 caches are in the core as specified in this link.
Also in the below CPU layouts we see L1 and L2 caches take place inside of the CPU together with pipeline stages and control units.
My question is does these data and instruction memory we see in the data path corresponds to the L1 Instruction and L1 Data cache inside of the core?
Yes, the load/store execution unit accesses L1d cache if the CPU has cache. And the instruction fetch unit accesses L1i, if the CPU has L1i cache. Or if it has a unified L1 like old P5 Pentium or older ARM, it accesses that. Most CPUs use split L1 caches (“modified Harvard”) instead of more read/write ports in a single unified L1d cache. But still one unified address-space for memory, not full Harvard where the same numerical address is different storage for code vs. data.
So anyway, the “data memory” block in the block diagram is a load/store execution unit in terms of a modern CPU like https://www.realworldtech.com/sandy-bridge/10/
On cache miss, an access to unified L2 will happen. And if it misses there, access L3 or DRAM. (Some CPUs only have two levels of cache. Some old CPUs only have one level.)
See also Modern Microprocessors
A 90-Minute Guide! for a good overview of how various concepts fit together.
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